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Verilog Program for Ring Counter with Test bench and Output 23 Jan 2013 | 07:14 pm
Ring counter is a sequential circuit made up of flip flops in which the output of the final flip flop is again fed back a input to the first flip flop. The shifting operation is controlled by the cloc...
The USB-Features and its Versions 14 Dec 2012 | 10:20 pm
What is USB ? USB stands for Universal Serial Bus. It eliminates need of add-in cards and separate power supplies and its hot swapping capability allows users to easily attach and detach peripherals.T...
Paper Battery Technology 11 Dec 2012 | 01:04 pm
The Idea !!! The revolutionary idea of using paper as a battery was striked to some researchers at Stanford University few yeas back and their experiments in this domain proved fruitful recently concl...
Verilog Program for Complex Adder/Subtractor and Complex Multiplier with Test bench 26 Oct 2012 | 04:00 pm
Complex Numbers are denoted in the form ” a+ib “ where a is the real part and b is the imaginary part. The basic rules of the complex numbers addition and multiplication are directly applicable here a...
Verilog Progam for Mealy and Moore Machines with test bench and Output 24 Oct 2012 | 10:35 am
There are two types of State machines: 1)Mealy Machine 2) Moore machine The Verilog code of both machines are given below. Execute them and analyze the difference. You can download the programs at the...
Verilog Program for Implementation of Logic Function with test bench 26 Sep 2012 | 10:57 pm
If you are given a logic equqtion, use the code below and implement the function: Here is the program: /* Verilog Program to implement the function f=x+y’z and Testbench for all the possible inputs us...
Verilog Program for 4:1 Multiplexer(MUX) with Test Bench and Output 26 Sep 2012 | 10:38 pm
Multiplexer is a electronic device which used to convert many to one. It transfers the multiple inputs to a single output line by selecting one of the inputs at a time with the help of selection line...
Verilog Program for Asynchronous D Flip Flop with Test Bench and Output 15 Sep 2012 | 06:51 pm
In a Asynchronous D Flip Flop, there is no direct synchronization between the clock and the ouput as the output will change at the instant when reset value changes. The output will not wait for the po...
Verilog program for Synchronous D Flip Flop with Test Bench and output 10 Sep 2012 | 09:40 pm
Synchronous D flip flop as its name suggests its output is synchronized with the positive edge or negative edge of the clock pulse. Verilog code for this flip flop along with the test bench is given b...
VeriLog Program for JK flip Flip with test bench and Output 9 Sep 2012 | 09:42 pm
Verilog program for JK flip flop with the test bench is as follows. Download the outputs attached at the end. /*JK flip flop Code by Anand Contact me at itsexzion@gmail.com */ module jk_ff(q,qn,j,k,cl...
